1. Technical Field
The invention relates to transistors and methods of forming the same, more particularly, to transistors having reinforcement layer patterns and methods of forming the same.
2. Discussion of the Related Art
Transistors are formed by using many technologies with a single crystal silicon base substrate in order to realize a very high speed current driving capability. One of the technologies involves the use of a semiconductor substrate having a relaxed silicon germanium (SiGe) layer and a strained silicon layer sequentially stacked on the single crystal silicon base substrate. The semiconductor substrate is prepared using the relaxed silicon SiGe layer and changing a lattice constant of a silicon layer to form the strained silicon layer. At this time, the strained silicon layer has a higher lattice constant than that of the single crystal silicon base substrate. This means that, in the case of using the strained silicon layer as a channel of the transistor with a normal design rule, carriers in the strained silicon layer can be moved at a higher speed than in the single crystal silicon base substrate.
Further, the semiconductor substrate has source and drain regions overlapping a gate pattern of the transistor. The source and drain regions are formed by performing an ion implantation process in the semiconductor substrate. At this time, impurity ions of the source and drain regions show different diffusion velocity in the strained silicon layer and the relaxed SiGe layer. That is, the impurity ions in the strained silicon layer have a lower diffusion rate than in the relaxed SiGe layer. This the semiconductor fabrication process to effectively adjust to the gradual reduction of the design rule. Therefore, the semiconductor fabrication process produces the transistor having a very high speed current drive capability by using the semiconductor substrate.
However, the strained silicon layer may be partially removed by physical or chemical attack during the semiconductor fabrication process. Also, since the strained silicon layer becomes thin due to the physical or chemical attack, it may fail to control the diffusion velocity of the impurity ions in the source and drain regions during the semiconductor fabrication process. Thus, the impurity ions of the source and drain regions may follow to a bulk diffusion velocity of the relaxed SiGe layer instead of a surface diffusion velocity of the strained silicon layer. As such, the source and drain regions contact each other under the gate pattern, thereby causing a punchthrough phenomenon of the transistor. As a result, the strained silicon layer, which is attacked during the semiconductor fabrication process, allows the transistor not to have such a very high speed current driving capability differently from an intention of an original semiconductor circuit interconnection layout.
On the other hand, U.S. Pat. No. 6,429,061 to Kern Lim (the '061 patent) discloses method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation.
According to the '061 patent, the method includes forming a relaxed SiGe layer on a surface of a substrate. Isolation regions and well implant regions are formed in the relaxed SiGe layer. A strained silicon layer is formed on the relaxed SiGe layer.
However, the method may cause a physical or chemical attack to the strained silicon layer during the semiconductor fabrication process. Thus, since the strained silicon layer becomes thin due to the physical or chemical attack, the strained silicon layer may not control the diffusion velocity of the impurity ions in the well implant regions. Thus, the attacked strained silicon layer may degrade electrical characteristics of the CMOS structure.